ALU

For our first implementation of logic locking, we did a simple ALU. We first wrote Verilog code for a simple 4-bit ALU. The ALU was implemented on the FPGA and tested by inspection for all cases. After verification, Verilog behavioral logic code was converted into specific structural code by Synopsys Design Tool. Library code for the modules of the structural code was to 32 nm standards, extracted into Verilog code in order to decode specific module names in the structural code. Structural code will be implemented on FPGA with expected results of exactly matching the result of the behavioral logic code. This Structural code is needed for the obfuscation algorithm as well as the flatten netlist it provides.  Next, obfuscation of structural ALU code will begin and specific gates will be selected for obfuscation. Structural code will be synthesized from this new obfuscated ALU and implemented on the FPGA and then checked for verification. The key will be 8 bits long, using the remaining switches on the Tpad board housing the FPGA.